A conventional inspection apparatus includes a prober chamber for performing inspection of electrical characteristics of, for example, semiconductor wafers and a loader chamber for performing a transfer of the semiconductor wafers one by one between a cassette and the prober chamber. A prober card and an alignment mechanism are disposed in the prober chamber. After a semiconductor wafer on a wafer chuck is aligned with the probe card by the alignment mechanism, the semiconductor wafer and the probe card are brought into electrical contact with each other, so that inspection of electrical characteristics of the wafer is carried out. Inside the loader chamber, there is provided a wafer transfer device which serves to transfer the semiconductor wafers between the cassette and the wafer chuck.
However, as the diameter of a semiconductor wafer increases over 300 mm, the size of the inspection apparatus becomes large, resulting in a cost increase due to a rapid enlargement of a space occupied by the inspection apparatus within a clean room as well as a cost increase of the inspection apparatus itself. Furthermore, with the trend toward the large diameter of the semiconductor wafer and high integration of semiconductor chips thereon, a time period during which the semiconductor wafer stays in the inspection apparatus increases, necessitating efficient manipulation of the semiconductor wafer.
Patent Reference 1 describes a prober apparatus having a configuration in which a plurality of wafer chucks in a prober unit shares a common alignment mechanism. In this prober apparatus, since a plurality of (for example, two) mounting tables share the single alignment mechanism, a cost reduction can be realized. Further, since inspection can be carried out at the plurality of wafer chucks simultaneously, a throughput can be improved as well.
Patent Reference 2 describes a wafer inspection apparatus which inspects semiconductor wafers one by one. In this wafer inspection apparatus, it is attempted to reduce an inspection time by way of performing a single-sheet process of transferring semiconductor wafers one by one between a cassette stocking portion and wafer inspection units by using a first and a second self-propelled carriage.
Moreover, Patent Reference 3 describes a glass substrate moving carriage which serves to perform a sampling test of a glass substrate in processing apparatuses. Since this glass substrate moving carriage includes a positioning and transferring device, a positioning and transferring device of each processing apparatus can be omitted, thus resulting in a reduction of a footprint of each processing apparatus.
(Patent Reference 1)
Japanese Patent Laid-open Application No. S63-062249
(Patent Reference 2)
Japanese Patent No. 3312748
(Patent Reference 3)
Japanese Patent Laid-open Application No. 2002-313870
As for the technique described in Patent Reference 1, however, since the alignment mechanism is fixed at a central position between the two wafer chucks and alignment of a wafer on each wafer chuck with a probe card is performed by moving each wafer chuck to a position directly under the alignment mechanism, a movement range of each wafer chuck is large and there is a limit in reducing the footprint.
In the technique of Patent Reference 2, though the semiconductor wafer single-sheet process may contribute to the reduction of the inspection time, the inspection units themselves have the substantially same configurations as that of the conventional inspection apparatus, and it is required to provide a space between the individual wafer inspection units. Thus, it is impossible to reduce the footprints of the wafer inspection units themselves. Further, the technique of Patent Reference 3 also requires provision of a space between the processing apparatuses.